Post-silicon measurement: characterizing chips circuit by circuit

Simulation tells you what a circuit should do; measurement tells you what it does. Post-silicon work turns a box of new chips into numbers you can trust: first that the chip is alive, then how each block performs across process, voltage, and temperature, and finally whether it will keep performing for years. This note is a practical guide to that work, organized circuit by circuit, with the equation behind each measurement and the mistakes that most often spoil it. It draws on the measurement material taught in university RF and mixed-signal courses and on the instrument makers' application notes listed at the end.

1The flow: bring-up to qualification

2Fixtures, calibration, and de-embedding

You never measure the chip alone; you measure the chip plus cables, probes or board, and package. Calibration moves the reference plane to where you want it.

• On-wafer: ground-signal-ground (GSG) probes on a probe station, calibrated on an impedance standard substrate with SOLT, LRRM, or TRL (Engen and Hoer, reference 4). TRL needs no perfectly known load, which is why it is preferred at mm-wave.
• De-embedding: on-chip pads add capacitance and the lines to the device add series impedance. Measuring dummy “open” and “short” structures and subtracting them (Koolen et al., reference 5) brings the reference plane to the device itself.
• Packaged parts: an evaluation board with controlled-impedance lines; de-embed the board with 2x-thru or matched fixture structures.

3The instruments

4LNAs and receivers

S-parameters and stability

Measure all four S-parameters across a band much wider than the operating band, because an amplifier can oscillate far from where it is used. Check unconditional stability with the Rollett factor or, more directly, the μ factor:

where $\Delta =S_{11}{S}_{22}-S_{12}{S}_{21}$.

Noise figure

The Y-factor method switches a calibrated noise source between “cold” (off, about 290 K) and “hot” (on, with an excess noise ratio ENR) and measures the output noise power in each state:

The analyzer's own noise is removed with a second-stage correction (Friis, in reverse). For very low noise figures, the cold-source method on a VNA avoids the noise source's mismatch change between hot and cold states. The background is in the noise figure note.

Linearity

• 1 dB compression (P1dB): sweep input power and find where gain has dropped 1 dB.
• Third-order intercept (IIP3): two equal tones at $f_1$, $f_2$ produce products at $2f_1-f_2$ and $2f_2-f_1$. With $\Delta P$ the difference between the output fundamental and the output IM3 in dB, $\text{IIP3}=P_{\text{in}}+\Delta P/2$. Check that IM3 rises 3 dB per dB of input; if not, you are measuring the analyzer or the source.

5Mixers

• Conversion gain from RF to IF across RF, LO, and IF frequencies and LO power.
• Noise figure: state whether it is single-sideband or double-sideband; DSB is about 3 dB lower for the same mixer.
• Isolation: LO-to-RF (LO leaking out of the antenna), LO-to-IF, and RF-to-IF.
• Linearity: IIP3 and, for direct-conversion receivers, IIP2, which sets how strongly a blocker's envelope appears at DC.
• Image rejection for image-reject architectures, set by I/Q gain and phase balance.

6Oscillators and PLLs

Phase noise $ℒ(\Delta f)$ is the single-sideband noise power in 1 Hz at offset $\Delta f$, relative to the carrier, in dBc/Hz. Integrating it gives rms jitter, and the standard figure of merit normalizes for frequency and power:

• Always state the integration limits $f_1$–$f_2$ with a jitter number; 10 kHz–100 MHz and 12 kHz–20 MHz are both common, and they give different answers.
• Also measure tuning range and gain (MHz/V), frequency pushing (versus supply) and pulling (versus load), PLL lock time, reference spurs, and fractional spurs.
• The reference and the instrument have phase noise too. The instrument's floor must be well below what you are measuring; cross-correlation analyzers lower it.

7Power amplifiers, reliability, and lifetime

Performance

• Continuous wave: output power, gain, drain efficiency, and PAE versus input power and frequency; harmonics.
• AM-AM and AM-PM: gain and phase versus input amplitude, the inputs to digital predistortion.
• Modulated signals: adjacent-channel leakage ratio (ACLR) and error vector magnitude (EVM) with the real standard's signal, at the average power and peak-to-average ratio it will see.
• Load-pull: tuners present different load impedances to map output power and efficiency contours, so you know where the optimum is and how far your match is from it.
• Thermal: junction temperature from thermal resistance, $T_j=T_{\text{case}}+{\theta }_{\text{jc}}(P_{\text{DC}}+P_{\text{in}}-P_{\text{out}})$. Every reliability model depends on it.

Ruggedness

A PA must survive a bad antenna: a phone held against metal, or a disconnected antenna. A ruggedness test drives the PA at maximum output into a load mismatch, commonly a voltage standing-wave ratio of 10:1, rotated through all phases, at high supply voltage, then checks that its performance has not changed.

What wears a PA out

How lifetime is measured

Nobody waits ten years. Devices are stressed harder than in use, at higher temperature, voltage, or RF drive, while a key parameter is logged. A common failure criterion for a PA is a 1 dB drop in output power or gain. The time to failure at stress is then translated to use conditions with acceleration models. For temperature, the Arrhenius model:

and for electromigration, Black's equation (reference 6), which adds current density:

• Use several stress levels (at least three temperatures or voltages) so the activation energy or voltage exponent is measured, not assumed. Reported GaN HEMT activation energies range from a fraction of an eV to over 2 eV depending on the mechanism and bias (reference 9).
• Use enough parts and fit the times to failure with a Weibull or lognormal distribution. Report a low percentile (time to 0.1% failures), not only the median.
• Stress with RF, not just DC. The voltage and current waveforms decide which mechanism dominates: in a switching (class-E) PA the drain voltage is high only while the current is near zero, so hot carriers matter less and oxide stress matters more. DC stress at the same average power can predict the wrong lifetime.
• Check that acceleration does not change the mechanism. Too much stress can trigger a failure that never happens in use. Failure analysis of stressed parts confirms the mechanism.

8Data converters

• Static: INL and DNL from a code-density (histogram) test with a slow ramp or a sine input, as defined in IEEE Std 1241 (reference 10).
• Dynamic: FFT of a sine input gives SNR, SNDR, THD, and SFDR. Effective number of bits:

• Coherent sampling: choose $f_{\text{in}}=(J/N)f_s$ with $J$ odd and coprime to the FFT length $N$, so every code is exercised and no window is needed.
• The jitter limit in eq. (7) is why a 10 GHz input needs a clock with less than about 50 fs of jitter for 50 dB SNR. Measure with a clean source and a band-pass filter on the input; the generator's harmonics are often worse than the converter's.

9High-speed links

• Transmitter: output swing, rise and fall times, return loss, FFE levels, and for PAM4 the level linearity (RLM); jitter decomposed into random (RJ) and deterministic parts (DJ: data-dependent, periodic, duty-cycle).
• Receiver: BER with PRBS patterns through reference channels; sensitivity; jitter tolerance, sweeping the frequency and amplitude of injected sinusoidal jitter against the standard's mask.
• Bathtub curves extrapolate BER versus sampling phase to 10⁻¹² and beyond without waiting days. With the dual-Dirac model, $\text{TJ}(\text{BER})=\text{DJ}+2Q(\text{BER}){\sigma }_{\text{RJ}}$ (IEEE Std 2414, reference 11).

10LDOs, converters, and references

• Load and line regulation: output change versus load current and input voltage, in steady state.
• Load transient: step the load with a fast electronic load or an on-board MOSFET and resistor; measure undershoot, overshoot, and settling with a short ground spring on the probe. A long ground lead adds inductive ringing that is not in the circuit.
• PSRR: inject a sine on the input (with an injector transformer or a modulated supply) and measure the ratio of input to output ripple versus frequency.
• Efficiency of switching converters versus load, with input and output power measured by separate meters at the pins, not by the supply's readout.
• Bandgap references: output versus temperature, reported with the box method, $\text{TC}=\frac{V_{\text{max}}-V_{\text{min}}}{V_{\text{nom}}(T_{\text{max}}-T_{\text{min}})}\times {10}^6$ ppm/°C; plus noise and line regulation. Measure many parts: the spread matters more than one curve.

11Optical and photonic circuits

• Photodiodes and receivers: responsivity (A/W), bandwidth with a lightwave component analyzer, dark current, and sensitivity: the optical modulation amplitude (OMA) needed for the target BER.
• Modulators and transmitters: extinction ratio, OMA, electro-optic bandwidth, V_π, and for PAM4 the transmitter dispersion and eye closure (TDECQ).
• Rings and filters: wavelength sweeps with a tunable laser and power meter; thermal tuning efficiency (nm/mW); see the notes on microrings and ring auto-tuning.
• Coupling loss to fiber changes with alignment and polarization; measure reference structures (loop-back waveguides) on every chip.

12Statistics, production test, and qualification

One good chip proves the design can work; a population shows whether it works. Report mean and standard deviation across parts, and the process capability index against each limit:

A $C_{\text{pk}}$ of 1.33 or more is a common target. Production test then checks each part quickly on ATE, with guard bands that cover the tester's own accuracy, often using built-in self-test and loopback to avoid expensive instruments.

With the Arrhenius figure above: 1000 h at 125 °C with $E_a=0.7$ eV is about 78,000 h, or roughly 9 years, at 55 °C.

13Lab habits that save weeks

• Measure something known first: a thru, a reference amplifier, a calibration structure. If that is wrong, nothing after it is right.
• Record everything: chip ID, board, supplies, temperature, instrument settings, calibration date, and cable set. Scripts with logged settings beat screenshots.
• Power up current-limited and in a planned sequence. Check currents against simulation before applying signals.
• Let things warm up (instruments and the chip) and wait for thermal settling after every change of bias.
• Change one thing at a time, and repeat a measurement on a second chip before believing a surprise.

Questions & answers

Should I measure on-wafer or packaged?

On-wafer for device and block characterization at high frequency, where the package would hide what you want to see, and for fast iteration. Packaged for system-level performance, thermal behavior, and anything the customer will see. Most projects need both, with test structures designed for each.

My measured noise figure is better than simulation. Should I celebrate?

Check first. Common causes are an uncorrected analyzer noise contribution, a wrong ENR table, mismatch between the noise source's hot and cold states, or a gain error that inflates Y. Re-measure with a different noise source or the cold-source method.

How many parts and lots do I need for a lifetime claim?

Qualification standards such as JESD47 specify sample sizes (for HTOL, typically 3 lots of 77 parts with zero failures). For modeling a wear-out mechanism, you need enough failures at each of several stress levels to fit a distribution, often 10–20 parts per condition.

Why does RF stress give a different lifetime than DC stress?

Because each mechanism responds to a different combination of voltage and current at the same instant. Under RF, the device swings through states it never sees at DC; for oxide wear, the rms field across the oxide is what counts (reference 8). Stress with waveforms that match operation.

Where can I learn this from a course?

MIT OpenCourseWare 6.776 (reference 1) covers the circuits and the noise and phase-noise background; the Keysight application notes (references 2 and 3) are the standard practical guides to noise figure and spectrum analysis, and Stanford's EE133 hosts the noise figure note for its lab.

Further reading

1. M. Perrott, 6.776 High Speed Communication Circuits, MIT OpenCourseWare, 2005. ocw.mit.edu
2. Keysight Technologies, “Fundamentals of RF and Microwave Noise Figure Measurements,” Application Note 57-1 (5952-8255E). PDF hosted by Stanford EE133
3. Keysight Technologies, “Spectrum Analysis Basics,” Application Note 150 (5952-0292). PDF
4. G. F. Engen and C. A. Hoer, “Thru-reflect-line: an improved technique for calibrating the dual six-port automatic network analyzer,” IEEE Trans. Microw. Theory Techn., vol. 27, no. 12, 1979. doi:10.1109/TMTT.1979.1129778
5. M. C. A. M. Koolen, J. A. M. Geelen, and M. P. J. G. Versleijen, “An improved de-embedding technique for on-wafer high-frequency characterization,” Proc. IEEE BCTM, 1991. doi:10.1109/BIPOL.1991.160985
6. J. R. Black, “Electromigration—a brief survey and some recent results,” IEEE Trans. Electron Devices, vol. 16, no. 4, 1969. doi:10.1109/T-ED.1969.16754
7. C. Hu et al., “Hot-electron-induced MOSFET degradation—model, monitor, and improvement,” IEEE J. Solid-State Circuits, vol. 20, no. 1, 1985. doi:10.1109/JSSC.1985.1052306
8. L. Larcher, D. Sanzogni, R. Brama, A. Mazzanti, and F. Svelto, “Oxide breakdown after RF stress: experimental analysis and effects on power amplifier operation,” Proc. IEEE IRPS, 2006. doi:10.1109/RELPHY.2006.251229
9. Chakraborty and Kim, “Reliability assessment of on-wafer AlGaN/GaN HEMTs: the impact of electric field stress on the mean time to failure,” Micromachines, vol. 14, 1833, 2023. doi:10.3390/mi14101833
10. IEEE Std 1241-2010, IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters. doi:10.1109/IEEESTD.2011.5692956
11. IEEE Std 2414-2020, IEEE Standard for Jitter and Phase Noise. doi:10.1109/IEEESTD.2021.9364950
12. JEDEC JESD47, Stress-Test-Driven Qualification of Integrated Circuits, and the JESD22 test methods it references (jedec.org).

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