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Note · SerDes

SerDes design: circuits, standards, and where to start

Ramy Rady · October 2026 · 18 min read

A SerDes (serializer–deserializer) moves a wide, slow parallel bus across a few fast wires and recovers every bit at the other end. It is the circuit behind PCIe, Ethernet, USB, DisplayPort, memory interfaces, and chiplet links. This note walks through an electrical I/O transceiver block by block: what each circuit does, the equation that sizes it, and the numbers that are typical today. It also maps the current standards and ends with a learning path: the books, papers, tools, and conferences I would start with.

1The job and the budget

Every link has the same structure: a transmitter (TX) serializes and drives the data, a channel (package, board traces, connectors, cable) distorts it, and a receiver (RX) equalizes, samples, and recovers both the clock and the data.

Figure 1. A SerDes link. The TX PLL clocks the serializer; on the receive side, the clock and data recovery (CDR) loop finds the sampling phase from the data itself.

Three numbers define the budget:

Data rate per lane, which sets the unit interval (UI): the time for one symbol, $UI = 1 / baud$ . At 112 Gb/s PAM4 (56 GBd) one UI is about 18 ps.
Bit error rate (BER): 10⁻¹² or better for NRZ links without forward error correction, and about 10⁻⁴ before correction for PAM4 links that use FEC.
Energy per bit: a few pJ/bit for long-reach 100G-class lanes, and well under 1 pJ/bit for short die-to-die links.

2Standards map

The table lists the electrical interfaces a SerDes designer meets most often, with per-lane rates. A standard fixes the rate, the modulation, the channel it must survive, and how compliance is measured; the circuits underneath are similar across families.

Family	Generation	Per-lane rate	Modulation	Notes
PCI Express	1.0 / 2.0	2.5 / 5 GT/s	NRZ	8b/10b coding
	3.0 / 4.0 / 5.0	8 / 16 / 32 GT/s	NRZ	128b/130b coding; 5.0 budgets about 36 dB loss at 16 GHz
	6.0	64 GT/s	PAM4	FLIT mode with lightweight FEC
	7.0	128 GT/s	PAM4	Specification released June 2025
	8.0	256 GT/s	PAM4	Announced August 2025, targeted for 2028
Ethernet (IEEE 802.3, electrical)	10GBASE-KR	10.3125 Gb/s	NRZ	backplane, 64b/66b
	25GBASE-KR	25.78125 Gb/s	NRZ	802.3by, RS-FEC optional
	50G per lane	53.125 Gb/s (26.56 GBd)	PAM4	802.3cd, RS(544,514) “KP4” FEC
	100G per lane	106.25 Gb/s (53.125 GBd)	PAM4	802.3ck; KR channels about 28 dB at Nyquist
	200G per lane	212.5 Gb/s (106.25 GBd)	PAM4	P802.3dj, completing in 2026
OIF CEI	CEI-28G, -56G, -112G, -224G	28 to 224 Gb/s	NRZ, PAM4	Implementation agreements for chip-to-chip, chip-to-module, and backplane reaches
USB / Thunderbolt	USB 3.2 Gen 1 / Gen 2	5 / 10 Gb/s	NRZ
	USB4 (Gen 3)	20 Gb/s	NRZ	two lanes per direction, 40 Gb/s
	USB4 v2, Thunderbolt 5	about 40 Gb/s	PAM3	80 Gb/s per direction; asymmetric mode up to 120 Gb/s
Display	DisplayPort 2.1	up to 20 Gb/s (UHBR20)	NRZ	4 lanes, 128b/132b
	HDMI 2.1 / 2.2	12 / 24 Gb/s	NRZ	4 lanes, FRL mode; 48 and 96 Gb/s total
	MIPI D-PHY v3.0	up to 9 Gb/s	NRZ (differential)	mobile display and camera
	MIPI C-PHY v2.1	up to 7.5 Gsym/s per trio	3-wire, 3-phase	about 2.28 bits per symbol
Memory	DDR5 / LPDDR5X	up to 8.8 / 10.7 Gb/s per pin	NRZ, single-ended	parallel buses with per-pin training
	GDDR6 / GDDR7	up to ~24 / 32+ Gb/s per pin	NRZ / PAM3	GDDR7 (JESD239) uses PAM3
	HBM3E	~9.6 Gb/s per pin	NRZ	1024-bit interface on an interposer
	HBM4	8 Gb/s per pin	NRZ	2048-bit interface, about 2 TB/s per stack (JESD270-4, April 2025)
Die-to-die	UCIe 1.x / 2.0 / 3.0	up to 32 / 32 / 64 GT/s	NRZ, single-ended	UCIe 3.0 (August 2025) adds 48 and 64 GT/s; short, unterminated or lightly terminated links
Storage, converters	SATA 3, SAS-4, JESD204C	6, 22.5, up to 32 Gb/s	NRZ	JESD204C links data converters to FPGAs and ASICs

Rates as published by PCI-SIG, IEEE 802.3, OIF, USB-IF, VESA, HDMI Forum, MIPI Alliance, JEDEC, and the UCIe Consortium, as of October 2026. Check the current specification before you design to one.

3Signaling: NRZ, PAM4, PAM3

NRZ sends one bit per symbol on two levels. PAM4 sends two bits per symbol on four levels, halving the symbol rate for the same bit rate, so the channel's loss at the Nyquist frequency (half the symbol rate) is much lower. The price is that each of its three stacked eyes is one third of the full swing:

{penalty}_{M -PAM} = 20 \log_{10} (M - 1) PAM4: 9.5 dB, PAM3: 6.0 dB

(1)

PAM4 wins when NRZ at twice the symbol rate would lose more than about 9.5 dB extra in the channel, which is the case for most links above about 50 Gb/s. PAM3 (three levels, 1.5 bits per symbol in practice) sits in between and is used by GDDR7 and USB4 v2.

4The channel

Board traces lose signal in two ways that both grow with frequency: conductor (skin-effect) loss, which grows as $\sqrt{f}$ , and dielectric loss, which grows as $f$ . A first-order model of insertion loss in dB per unit length is

α (f) \approx a_{1} \sqrt{f} + a_{2} f a_{2} \propto \sqrt{ε_{r}} \tan δ

(2)

A link is specified by its loss at the Nyquist frequency. Low-loss laminates (dissipation factor $\tan δ$ around 0.002–0.005 compared with about 0.02 for FR-4) are what make long-reach 100G and 200G lanes possible. On top of loss come:

Reflections from impedance discontinuities: vias, connectors, package balls, and via stubs, which create sharp notches at $f = v / (4 l_{stub})$ . Back-drilling removes stubs.
Crosstalk, near-end (NEXT) and far-end (FEXT), from neighbouring lanes.
Inter-symbol interference (ISI): the pulse response spreads over many UIs, so each received sample contains pieces of earlier and later symbols. Equalization exists to undo this.

5Transmitter

Serializer

A tree of 2:1 multiplexers converts the parallel word into one stream. Only the last stage runs at full rate, so most designs use half-rate or quarter-rate clocks: the final mux selects between two inputs on both clock edges. Duty-cycle error in that clock appears directly as jitter on the output.

Driver: current mode or voltage mode

	Current-mode logic (CML)	Voltage-mode (source-series terminated, SST)
How it works	Steers a tail current between two 50 Ω loads	Switches each output between the rails through a resistance that also forms the 50 Ω termination
Swing	$V_{pp,diff} = I_{tail} \times 50 Ω$ with a 50 Ω far-end load	up to $V_{DD}$ differential peak-to-peak
Power for the same swing	reference	about 4× lower supply current
Strengths	Good supply rejection, easy high-swing at high speed	Efficient, scales with CMOS; FFE by segmenting the driver

Feed-forward equalization (FFE)

The TX pre-distorts each symbol with a short FIR filter so that, after the channel, the pulse is narrower:

y [n] = c_{- 1} d [n + 1] + c_{0} d [n] + c_{1} d [n - 1], | c_{- 1} | + | c_{0} | + | c_{1} | = 1

(3)

The taps share a fixed peak swing, so FFE equalizes by attenuating the low frequencies rather than boosting the high ones (“de-emphasis”). A single post-cursor tap $c_{1} = - 0.25$ lowers the steady-state level to half the transition level: 6 dB of de-emphasis. At 112 Gb/s and above, the TX is usually a 6–8 bit DAC driven by a digital FIR with more taps.

6Receiver and equalization

Continuous-time linear equalizer (CTLE)

The CTLE is a high-pass shaped amplifier: a source-degenerated differential pair whose degeneration capacitor creates a zero below the poles.

H (s) = A_{0} \frac{1 + s / ω_{z}}{(1 + s / ω_{p 1}) (1 + s / ω_{p 2})}, peaking \approx \frac{ω_{p 1}}{ω_{z}}

(4)

For a degenerated pair with transconductance $g_{m}$ , degeneration $R_{S}$ , and $C_{S}$ : the zero is at $1 / (R_{S} C_{S})$ and the peaking is about $1 + g_{m} R_{S} / 2$ . A CTLE also boosts high-frequency noise and crosstalk, which is why it is rarely asked for more than 10–15 dB.

Decision-feedback equalizer (DFE)

Once a symbol is decided, its contribution to later samples is known. The DFE subtracts it:

z [n] = x [n] - \sum_{k = 1}^{N} h_{k} \hat{d} [n - k]

(5)

Because it works on noiseless decisions, a DFE removes post-cursor ISI without amplifying noise, unlike a CTLE.
It cannot remove pre-cursor ISI, and a wrong decision is fed back as extra ISI (error propagation, usually bursts of a few bits).
The first tap must settle within one UI. Designs meet this with loop unrolling (speculation): two comparators precompute the result for each possible previous bit, and a mux picks one.

Samplers and ADC-based receivers

The decision is made by a regenerative latch, typically a StrongARM comparator, clocked at the center of the eye. Above about 100 Gb/s, most receivers replace the analog DFE with a time-interleaved ADC of 6–8 bits followed by a DSP that runs an FFE, a short DFE, and sometimes a maximum-likelihood detector. The ADC approach trades power for robustness to very lossy channels and easy adaptation.

7Clocking and clock recovery

Transmit clock

A PLL multiplies a reference to the line rate (or half or quarter of it). LC-tank VCOs have much lower phase noise than ring oscillators and are used for the fastest lanes; ring oscillators are smaller and tune wider. The PLL's integrated jitter has to fit in a small fraction of the UI: at 112 Gb/s PAM4 a total jitter budget of a few hundred femtoseconds rms is typical.

Clock and data recovery (CDR)

The receiver has no clock wire; it extracts one from the data transitions.

Bang-bang (Alexander) phase detector: samples at the data center and at the edge. If the edge sample matches the previous bit, the clock is late; if it matches the next bit, it is early. Simple and fast, but its gain depends on jitter, so the loop is nonlinear.
Phase-interpolator CDR: mixes quadrature phases of the PLL clock to rotate the sampling phase digitally; a digital loop filter drives it. Common in multi-lane designs that share one PLL.
Mueller–Müller detector: works from baud-rate samples alone by balancing the pulse response's first pre- and post-cursors. The natural choice for ADC-based receivers.

The CDR loop bandwidth (often around the baud rate divided by a few thousand) sets how much low-frequency jitter it tracks. Two specifications check it: jitter tolerance, the sinusoidal jitter amplitude the receiver survives versus frequency, and jitter transfer for retimers.

8Calibration, adaptation, and ESD

Termination calibration: on-chip resistors vary by ±20% across process; a replica is compared with an external precision resistor and trimmed, so the 50 Ω termination holds to a few percent.
Offset calibration: comparator and CTLE offsets are cancelled at start-up, otherwise they shift the decision threshold and close the eye.
Adaptation: FFE, CTLE, and DFE settings are adapted to the channel, usually with sign-sign LMS: $c_{k} \leftarrow c_{k} + μ sgn (e [n]) sgn (d [n - k])$ , where $e$ is the error between the sample and its ideal level.
Eye monitors: an extra sampler sweeps phase and threshold to map the eye inside the chip, which is invaluable when a link fails in a system.
ESD and pad capacitance: the ESD diodes and pad add a few hundred femtofarads that limit bandwidth. T-coils (bridged inductors) split that capacitance and cancel much of its effect.

9How links are verified

Channel simulation: statistical and bit-by-bit simulation with IBIS-AMI models of the TX and RX and S-parameters of the channel.
Channel Operating Margin (COM): the IEEE 802.3 figure of merit that combines channel S-parameters with reference TX and RX models into one signal-to-noise number; a channel passes with COM ≥ 3 dB.
Lab: PRBS patterns (PRBS7 for quick checks, PRBS31 for stress), a BERT, a sampling or real-time oscilloscope, jitter injection for tolerance, and on-chip loopback. The note on post-silicon measurement covers this in detail.

10Design numbers

Quantity	Rule
Unit interval	$UI = 1 / baud$ ; 25 Gb/s NRZ → 40 ps; 112 Gb/s PAM4 → 17.9 ps
Nyquist frequency	baud / 2; the fastest pattern 1010… is a sine at this frequency
PAM eye penalty	$20 \log_{10} (M - 1)$ : PAM4 9.5 dB, PAM3 6 dB
Q for BER	BER 10⁻¹² ↔ Q ≈ 7.0; 10⁻¹⁵ ↔ Q ≈ 7.9
Total jitter	$TJ = DJ + 2 Q σ_{RJ}$ ; RJ counts ≈ 14× its rms value at 10⁻¹²
Delay on FR-4	≈ 6–7 ps/mm, so one 18 ps UI fits in about 3 mm of trace
Driver efficiency	voltage-mode ≈ ¼ of the current of CML for the same swing
FFE de-emphasis	$20 \log_{10} (1 / (1 - 2 \| c_{1} \|))$ dB for a 2-tap FFE

11Learning path and resources

This is the list I would hand to someone new to the field, in roughly the order I would read it.

A learning order that works

The channel. Loss, reflections, crosstalk, and why a 100 Gb/s pulse doesn't survive a backplane.
Modulation and equalization. NRZ and PAM4, then CTLE, FFE, and DFE, and what each one can and cannot fix.
Clocking and clock recovery. PLLs, jitter, and how the receiver finds the right moment to sample.
Circuits. Transmitter drivers, receiver front ends, samplers, and ADC-based receivers.
Link budgets and standards. How everything above turns into a pass or fail against a specification.

Start here: overviews

M. Horowitz, C.-K. K. Yang, and S. Sidiropoulos, “High-speed electrical signaling: overview and limitations,” IEEE Micro, 1998. Short, and still the best single overview of why links are hard.
V. Stojanović and M. Horowitz, “Modeling and analysis of high-speed links,” IEEE CICC, 2003. How to think about a link as a system, including noise and jitter budgets.
S. Palermo, ECEN 720 “High-Speed Links Circuits and Systems” lecture notes, Texas A&M University. A full course that walks from channels to equalizers and CDRs, with references at the end of each lecture.
Magazine columns: B. Razavi’s “A Circuit for All Seasons” and A. Sheikholeslami’s “Circuit Intuitions” in IEEE Solid-State Circuits Magazine. Short, readable explanations of one building block at a time.

Books

Book	Best for
W. J. Dally and J. W. Poulton, Digital Systems Engineering, Cambridge University Press, 1998	Signaling, noise, timing, and the system view of links
B. Razavi, Design of Integrated Circuits for Optical Communications, 2nd ed., Wiley, 2012	TIAs, limiting amplifiers, CDRs, drivers; useful for electrical links too
B. Razavi, Design of CMOS Phase-Locked Loops, Cambridge University Press, 2020	PLLs and oscillators from first principles
B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017	The analog foundation everything else assumes
F. M. Gardner, Phaselock Techniques, 3rd ed., Wiley, 2005	Loop dynamics, acquisition, and phase-detector theory
M. P. Li, Jitter, Noise, and Signal Integrity at High-Speed, Prentice Hall, 2007	Jitter decomposition, BER, and how specifications are written
E. Bogatin, Signal and Power Integrity — Simplified, 3rd ed., Prentice Hall, 2018	An intuitive introduction to channels, impedance, and S-parameters
H. Johnson and M. Graham, High-Speed Digital Design: A Handbook of Black Magic, Prentice Hall, 1993	Practical board-level signal integrity

Key papers: equalization

J. L. Zerbe et al., “Equalization and clock recovery for a 2.5–10-Gb/s 2-PAM/4-PAM backplane transceiver cell,” IEEE JSSC, 2003. A complete transceiver with both NRZ and PAM4, explained end to end.
J. F. Bulzacchelli et al., “A 10-Gb/s 5-tap DFE/4-tap FFE transceiver in 90-nm CMOS technology,” IEEE JSSC, 2006. A clear example of FFE and DFE working together, including how the DFE’s first-tap timing is met.

Key papers: clocking and clock recovery

J. D. H. Alexander, “Clock recovery from random binary signals,” Electronics Letters, 1975. The bang-bang phase detector still used in most CDRs.
K. H. Mueller and M. Müller, “Timing recovery in digital synchronous data receivers,” IEEE Transactions on Communications, 1976. The baud-rate phase detector behind many ADC- and DSP-based receivers.
J. Savoj and B. Razavi, “A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector,” IEEE JSSC, 2001.
J. Lee, K. S. Kundert, and B. Razavi, “Analysis and modeling of bang-bang clock and data recovery circuits,” IEEE JSSC, 2004. How to predict jitter tolerance and jitter generation for a nonlinear loop.
A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE JSSC, 1998.
K. Kundert’s papers on jitter and PLL noise at The Designer’s Guide Community. Free and practical.

Standards documents

Standards turn all of this into numbers. Reading the electrical sections, even partially, shows what a real design has to meet.

OIF Common Electrical I/O (CEI) implementation agreements (oiforum.com). Free to download, and the clearest specifications for chip-to-chip and chip-to-module links.
IEEE 802.3 Ethernet (ieee802.org/3). The 100G- and 200G-per-lane electrical specifications, plus public task-force presentations that explain why each limit was chosen.
PCI Express base specification (pcisig.com). Available to PCI-SIG members; many conference tutorials summarize the electrical layer.

Tools for building intuition

PyBERT. An open-source Python link simulator with CTLE, FFE, DFE, and CDR models. The fastest way to see equalization at work.
Channel Operating Margin (COM). The IEEE 802.3 reference MATLAB code that turns a channel into a pass or fail figure. Running it on public channels shows how standards judge a link.
Public channel data. IEEE 802.3 task forces post measured backplane and cable S-parameters that you can load into PyBERT, COM, or your own scripts.
scikit-rf. A Python library for reading, plotting, and cascading S-parameters.

Where new work appears

Conferences: ISSCC (wireline sessions, tutorials, and short courses), the Symposium on VLSI Technology and Circuits, CICC, ESSERC (formerly ESSCIRC), and DesignCon for the signal-integrity side. OFC covers optical links.
Journal: the IEEE Journal of Solid-State Circuits, which publishes extended versions of the best conference papers.

Questions & answers

Why not just use a CTLE with more peaking instead of a DFE?

A CTLE boosts noise and crosstalk along with the signal at high frequency, so past 10–15 dB of peaking the SNR stops improving. A DFE cancels post-cursor ISI using clean decisions and adds no noise, which is why long-reach receivers combine a moderate CTLE with a DFE or a DSP.

What limits how fast a DFE can run?

The first tap: the decision for bit n has to be fed back and subtracted before bit n+1 is sampled, all within one UI. Loop unrolling removes the first tap from the critical path at the cost of doubling the comparators (four times for PAM4).

Why does PAM4 need FEC when NRZ often does not?

With a 9.5 dB eye penalty, PAM4 links run at raw error rates around 10⁻⁵ to 10⁻⁴. A Reed–Solomon code such as RS(544,514) corrects those errors to well below 10⁻¹², at the cost of a few percent overhead and about 100 ns of latency.

How should I choose the CDR loop bandwidth?

Wide enough to track low-frequency jitter and spread-spectrum clocking in the incoming data, narrow enough to filter high-frequency jitter and keep the loop stable with its latency. Most standards define a jitter-tolerance mask that sets the lower limit directly.

Can I try these ideas without lab equipment?

Yes. Move the sliders in the eye diagram above, then use PyBERT with a public channel file from the IEEE 802.3 archives. You can see the effect of every equalizer on a realistic channel in minutes.

I come from RF design. What transfers, and what is new?

Transmission lines, S-parameters, matching, noise and linearity all transfer directly. What is new is thinking in the time domain: pulse responses, inter-symbol interference, jitter budgets, and bit error rates. Start with the overview papers in section 11, then the equalization papers.

Do I need the full standards documents?

Not to start. Public overviews, the OIF implementation agreements, and the IEEE 802.3 electrical clauses are enough to learn how compliance is defined. Get the full documents when you design to one specific standard.

1The job and the budget✎Edit

2Standards map✎Edit

3Signaling: NRZ, PAM4, PAM3✎Edit

4The channel✎Edit

5Transmitter✎Edit