📡 mm-Wave CMOS & Photonic Hybrid Receiver Systems

Next-generation 5G/6G communication systems

Overview

This project explored hybrid electronic-photonic receiver architectures that combine CMOS mm-Wave front-ends with photonic signal processing to achieve wideband tunability and high blocker rejection. By leveraging the low-loss and high-bandwidth properties of photonic links alongside the integration density of CMOS, the resulting systems target next-generation 5G/6G communication receivers.

Problem

Conventional all-electronic mm-Wave receivers face fundamental trade-offs between bandwidth, noise figure, and blocker rejection. At frequencies above 20 GHz, achieving >30 dB blocker rejection while maintaining wide tuning range requires either large die area or significant power consumption. Integrating photonic components opens a new design space but introduces new challenges in RF-photonic interface design and phase noise management.

Approach

The receiver architecture uses an electro-optic modulator to up-convert the RF signal into the optical domain, where a photonic filter performs high-selectivity band selection before a photodetector recovers the baseband signal. The diagram below shows the signal chain:

RF In Modulator Photonic Filter Photodetector RF Out

The CMOS front-end was co-designed with the photonic filter to minimize interface loss. A tunable laser source and integrated thermo-optic tuning circuit allow dynamic center-frequency selection across the full mm-Wave band.

My Contributions

  • Designed the CMOS low-noise amplifier and modulator driver for the RF-photonic interface
  • Developed the photonic filter tuning algorithm integrated with the CMOS control loop
  • Simulated and characterized the hybrid receiver noise figure and blocker rejection
  • Built and tested prototype boards combining discrete CMOS and photonic components
  • Contributed to system-level modeling comparing all-electronic and hybrid architectures

Results

  • Demonstrated 20 GHz+ instantaneous bandwidth in characterization
  • Achieved up to 60% efficiency improvement over the all-electronic reference design
  • Measured >30 dB blocker rejection at the photonic filter output
  • System noise figure remained competitive with state-of-the-art CMOS-only solutions

Tools & Stack

  • TSMC 65nm CMOS process for LNA and driver design
  • Cadence Virtuoso / Spectre for circuit simulation
  • Silicon photonic test platform (microring-based tunable filter)
  • Keysight vector signal analyzer and signal generator for RF characterization
  • Python for measurement automation and data analysis

Notes

Some circuit-level details are withheld. Published results reference prototype characterization data.

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