🌐 High-Speed Optical Receiver Front-Ends

Ultra-low-power CMOS optical receivers for data centers

Overview

This project designed ultra-low-power, high-bandwidth CMOS optical receiver front-ends for data center and telecom interconnects. Optical receivers convert photocurrent from a photodetector into a digital signal, requiring a transimpedance amplifier (TIA) with high gain-bandwidth product and low input-referred noise. The goal was to achieve 100+ Gb/s throughput while significantly reducing power consumption compared to state-of-the-art commercial solutions.

Problem

As data center bandwidth demands grow, optical receiver power budgets are tightly constrained. Existing TIA designs trade power for bandwidth, making it difficult to simultaneously achieve >100 Gb/s operation and <10 mW power at competitive sensitivity levels. Additionally, process and temperature variation degrade receiver performance, necessitating on-chip calibration.

Approach

A regulated-cascode TIA topology was selected for its high bandwidth efficiency. The design used inductive peaking and bandwidth extension techniques to push the 3dB frequency beyond 70 GHz in simulation. An integrated automatic gain control (AGC) loop was added to maintain sensitivity across a wide input power range. The signal path is shown below:

Photodetector TIA Limiting Amp CDR Data Out

My Contributions

  • Designed the regulated-cascode TIA with inductive peaking for bandwidth extension
  • Implemented the automatic gain control (AGC) loop for wide dynamic range operation
  • Simulated noise, bandwidth, and sensitivity across process-voltage-temperature corners
  • Benchmarked against published state-of-the-art optical receivers in journals
  • Developed layout floor plan minimizing parasitic capacitance at TIA input node

Results

  • Demonstrated 100+ Gb/s data throughput capability in simulation and prototype testing
  • Achieved up to 50% power savings vs. baseline commercial reference design
  • Input sensitivity as low as <1 pA/√Hz in characterization
  • AGC maintained eye opening across >20 dB input power range

Tools & Stack

  • Advanced CMOS process node (node details withheld)
  • Cadence Virtuoso / Spectre for schematic entry and transient/noise simulation
  • Calibre for LVS/DRC verification
  • Python for measurement automation and eye diagram analysis
  • Oscilloscope (Keysight UXR series) and BERT for bit-error-rate testing

Notes

Some circuit details are withheld. Results reflect simulation and prototype characterization data.

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